In recent times, a main issue in the field of semiconductor memories has changed from an integration degree to an operation speed. Therefore, a high speed synchronous memory such as a Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) and a RAMBUS DRAM is a general trend in the field of the semiconductor memories
Synchronous memory refers to a memory which operates in synchronization with an external clock, and includes, for example, SDRAM, which is in a main stream of a commercial memory market in DRAMs. Input/output operation of the SDRAM is synchronized with a rising edge of an external clock and data access is performed once every clock period. However, data input/output operation of a DDR SDRAM is synchronized with not only the rising edge but also a falling edge of the external clock and data access is performed twice every clock period. That is to say, the DDR SDRAM has a data input/output speed which is two times as fast as that of the conventional SDRAM. Therefore, a high speed semiconductor memory device like the DDR SDRAM generates a clock which is enabled at a rising edge time of an external clock (hereinafter, referred to as a rising clock rclk) and a clock which is enabled at a falling edge time of the external clock (hereinafter, referred to as a falling clock fclk) in order to output data upon read operation.
FIG. 1 is a block diagram showing the structure of a conventional circuit for generating an internal circuit.
As shown in FIG. 1, the internal clock generating circuit to includes an enabling signal generating unit 1 which receives a read pulse signal RDP, a write/read status signal WTRD and an all bank precharge flag signal BANKALL and generates a clock enabling signal clkenb, and a clock generating unit 2 which generates rising and falling clock signals rclk, fclk in response to the clock enabling signal clkenb.
The enabling signal generating unit 1 generates a clock enabling signal clkenb at a low level by the read pulse signal which is applied as a pulse upon the read operation, and the clock generating unit 2 receiving the clock enabling signal clkenb at a low level generates the rising and falling clock signals rclk, fclk. The rising and falling clock signals rclk, fclk are used to output data to a DQ pad (not shown) upon the read operation and are used only in the read operation.
However, the conventional internal clock generating clock stops generation of the rising and falling clock signals rclk, fclk when a write operation begins or a semiconductor device memory is in an all bank precharge state in which the banks of the semiconductor memory device are all precharged. That is to say, the enabling signal generating unit generates a clock enabling signal clkenb at a high level by the write/read status signal WTRD which is shifted to a low level upon write operation and the all bank precharge flag signal BANKALL which is shifted to a high level in an all bank precharge state, and the clock generating unit 2 stops the generation of the rising and falling clock signals rclk, fclk.
Accordingly, the conventional internal clock generating circuit continuously generates the rising and falling clock signals rclk, fclk when the write operation does not begin or the semiconductor memory device is not in the all bank precharge state though the read operation is ended, and this causes an increase in current consumption.